1. Field of the Invention
This invention generally relates to hardware description language programming and, more particularly to a method for automatically converting software for single-channel hardware modules to multi-channel modules.
2. Description of the Related Art
As noted in Wikipedia, the semiconductor and electronic design industry uses Verilog, a hardware description language (HDL) to model electronic systems. Verilog HDL and equivalent languages are most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits.
Hardware description languages such as Verilog differ from software programming languages because they include ways of describing the propagation of time and signal dependencies (sensitivity). There are two assignment operators, a blocking assignment (=), and a non-blocking (<=) assignment. The non-blocking assignment allows designers to describe a state-machine update without needing to declare and use temporary storage variables. In any general programming language some temporary storage spaces are defined for the operands to be operated on subsequently; those are temporary storage variables. Since these concepts are part of Verilog's language semantics, designers can quickly write descriptions of large circuits, in a relatively compact and concise form.
A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and communicate with other modules through a set of declared input, output, and bidirectional ports. Internally, a module can contain any combination of the following: net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks, and instances of other modules (sub-hierarchies). Sequential statements are placed inside a begin/end block and executed in sequential order within the block. But the blocks themselves are executed concurrently, qualifying Verilog as a dataflow language.
Timeslicing is a technique used in digital designs in order to run multiple independent streams of data through the same RTL block. Each stream is assigned a channel number and a percentage of the available time slots. From an external observer's view point it appears as though there are multiple RTL engines each processing one channel. However, internally there is only one engine that keeps switching states every time a new channel's data come in—something that can happen as often as once per clock cycle.
Conventional timeslicing methods are not automated. All conversion needs to be done manually, which has a number of obvious disadvantages, as it requires a lot more time to implement. Manual implementation is subject to designer errors, requiring additional verification and debugging time. Once the conversion has been done manually, one can't go back to the single channel code, make changes, and easily apply these changes to the timesliced code.
Conventional methods do not treat the entire design as a single flat module. Instead they use the “channel id pipelining” technique, which means that every individual block in the design operates on a different channel at each clock cycle. Each block in the internal pipeline processes one channel's data and sends this data along with the channel number to the next block. The disadvantages of this approach are many, depending on the design, as it may greatly increase the complexity of the conversion. This approach fails and tedious workarounds are necessary when dependencies exist between pipeline stages, like feed backward and feed forward information, or dependencies on constant delays between pipeline stages. Verification also becomes a lot harder, as at any given point in time data from multiple channels coexists inside the design.
FIG. 1 is a schematic block diagram illustrating a central problem associated with timeslice conversion (prior art). In a timesliced design, each piece of input/output data is associated with a channel id. For example, data “IN1” becomes associated with channel “CID1”, and data IN2 associated with channel “CID2”, etc. Each channel's I/O when viewed independently should match the single channel operation. The main problem is dealing with the state of each module. At each clock cycle, the current state has to be saved into memory (RAM) and the next state loaded from memory.
It would be advantageous if timeslice conversion could be performed automatically, without manual interpretation.